Top 66 IEEE Transactions on Semiconductor Manufacturing papers published in 1998
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Showing papers in "IEEE Transactions on Semiconductor Manufacturing in 1998"
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Journal Article• 10.1109/66.705370•
MengChu Zhou 1•Institutions (1)
New Jersey Institute of Technology 1
01 Aug1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: A formal approach such as Petri nets enables one to describe such complex discrete event systems precisely and thus allows one to perform both qualitative and quantitative analysis, scheduling and discrete-event control of them.
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Abstract: This paper presents a Petri net approach to modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems. These systems can be characterized as discrete event systems that exhibit sequential, concurrent, and conflicting relations among the events and operations. Their evolution is dynamic over time. The system complexity is tremendous owing to the complex semiconductor manufacturing processes and test procedures. A formal approach such as Petri nets enables one to describe such complex discrete event systems precisely and thus allows one to perform both qualitative and quantitative analysis, scheduling and discrete-event control of them. This paper also serves as a tutorial paper. It briefly reviews applications of Petri nets in semiconductor manufacturing automation. It then introduces definitions and concepts of Petri nets. It proceeds with a discussion of basic Petri net modules in system modeling, a modeling method and a practical system's modeling example. Next, the paper presents their properties and their implications in manufacturing systems, as well as their analysis methods. Timed Petri nets are introduced for system simulation, performance evaluation, and scheduling purposes. An application-oriented case study is presented. Finally, the paper concludes with the active research areas in applying Petri nets to design of semiconductor manufacturing systems.
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300 citations
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Journal Article• 10.1109/66.661292•
Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing
B.E. Stine 1, Dennis Ouma 1, R. Divecha 1, Duane S. Boning 1, J.E. Chung 1, D. L. Hetherington 2, C.R. Harwoo, O.S. Nakagawa 3, Soo-Young Oh 3 - Show less +5 more•Institutions (3)
Massachusetts Institute of Technology 1, Sandia National Laboratories 2, Hewlett-Packard 3
01 Feb1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: New test mask designs and associated measurement and analysis methods are presented to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects.
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Abstract: Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.
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157 citations
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Journal Article• 10.1109/66.705373•
Scheduling of semiconductor test facility via Petri nets and hybrid heuristic search
Huanxin Henry Xiong 1, MengChu Zhou•Institutions (1)
TL;DR: Two Petri net-based hybrid heuristic search strategies are presented that combine the heuristic best-first strategy with the controlled back tracking strategy based on the execution of the Petri nets to cope with the complexities for multiple lots scheduling.
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Abstract: This paper proposes and evaluates two Petri net-based hybrid heuristic search strategies and their applications to semiconductor test facility scheduling. To reduce the setup time, such as the time spent to bring the test facilities to the required temperatures, scheduling multiple lots for each job type together is desirable. Petri nets can concisely model multiple lot sizes for each job, the strict precedence constraints, multiple kinds of resources, concurrent activities and flexible routes. To cope with the complexities for multiple lots scheduling, this paper presents two Petri net-based hybrid heuristic search strategies. They combine the heuristic best-first strategy with the controlled back tracking strategy based on the execution of the Petri nets. The obtained scheduling results are compared and analyzed through a small-size test facility. The better algorithm is also applied to a more sizable facility containing types of resources with a total of 79 pieces and 30 jobs. The future work includes the real-time implementation of the proposed method and scheduling results in real industrial settings.
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153 citations
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Journal Article• 10.1109/66.661288•
Model reduction for optimization of rapid thermal chemical vapor deposition systems
A. Theodoropoulou 1, Raymond A. Adomaitis 1, Evanghelos Zafiriou 1•Institutions (1)
University of Maryland, College Park 1
TL;DR: In this article, a model of a three-zone rapid thermal chemical vapor deposition (RTCVD) system is developed to study the effects of spatial wafer temperature patterns on polysilicon deposition uniformity.
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Abstract: A model of a three-zone rapid thermal chemical vapor deposition (RTCVD) system is developed to study the effects of spatial wafer temperature patterns on polysilicon deposition uniformity. A sequence of simulated runs is performed, varying the lamp power profiles so that different wafer temperature modes are excited. The dominant spatial wafer thermal modes are extracted via proper orthogonal decomposition and subsequently used as a set of trial functions to represent both the wafer temperature and deposition thickness. A collocation formulation of Galerkin's method is used to discretize the original modeling equations, giving a low-order model which loses little of the original, high order model's fidelity. We make use of the excellent predictive capabilities of the reduced model to optimize power inputs to the lamp banks to achieve a desired polysilicon deposition thickness at the end of a run with minimal deposition spatial nonuniformity. Since the results illustrate that the optimization procedure benefits from the use of the reduced-order model, our future goal is to integrate the model reduction methodology into real-time and run-to-run control algorithms. While developed in the context of optimizing a specific RTP process, the model reduction techniques presented in this paper are applicable to other materials processing systems.
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133 citations
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Journal Article• 10.1109/66.661295•
Yeong-Dae Kim 1, Jung-Ug Kim, Seung-Kil Lim, Hong-Bae Jun•Institutions (1)
KAIST 1
TL;DR: In this paper, the authors focus on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows and develop new dispatching rules for lot release and scheduling considering special features of the wafer fabrication process.
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Abstract: This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of processing waiting lots in front of workstations for lot scheduling. New dispatching rules are developed for lot release control and scheduling considering special features of the wafer fabrication process. Simulation experiments are carried out to test the dispatching rules. Results show that lot release control and lot scheduling at photolithography workstations are more important than scheduling at other workstations. Also, it is shown that new dispatching rules work better in terms of tardiness of orders than existing rules such as the EDD (earliest due date) rule and other well-known dispatching rules for multimachine scheduling.
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122 citations
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Journal Article• 10.1109/66.670175•
Nonlinear model reduction strategies for rapid thermal processing systems
Suman Banerjee 1, J. V. Cole 1, Klavs F. Jensen 1•Institutions (1)
Massachusetts Institute of Technology 1
01 May1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: In this paper, a method for developing low-order nonlinear models from physically based, large scale finite element models of rapid thermal processing (RTP) systems is presented, where low order models are extracted from transient results of a detailed finite element model using the proper orthogonal decomposition (POD) method.
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Abstract: We present a systematic method for developing low order nonlinear models from physically based, large scale finite element models of rapid thermal processing (RTP) systems. These low order models are extracted from transient results of a detailed finite element model using the proper orthogonal decomposition (POD) method. Eigenfunctions obtained from the POD method are then used as basis functions in spectral Galerkin expansions of the governing partial differential equations solved by the finite element model to generate the reduced models. Simulation results with the reduced order models demonstrate good agreement with steady state and transient data generated from the finite element model, with an order of magnitude reduction in execution time.
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70 citations
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Journal Article• 10.1109/66.670176•
Run by run advanced process control of metal sputter deposition
Taber H. Smith 1, Duane S. Boning 1, Jerry A. Stefani 2, Stephanie W. Butler 1•Institutions (2)
Massachusetts Institute of Technology 1, Texas Instruments 2
TL;DR: In this article, Run by Run (RbR) model-based process control (MBPC) has been applied to metal sputter deposition processes at Texas Instruments to track and compensate for process drifts without a priori assumptions on their magnitude or consistency.
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Abstract: Metal sputter deposition processes for semiconductor manufacturing are characterized by a decrease in deposition rate from run to run as the sputter target degrades. The goal is to maintain a desired deposition thickness from wafer to wafer and lot to lot. Run by run (RbR) model-based process control (MBPC) has been applied to metal sputter deposition processes at Texas Instruments. RbR MBPC, based on the exponentially weighted moving-average filter, provides the ability to track and compensate for process drifts without a priori assumptions on their magnitude or consistency (from sputter target to sputter target or collimator to collimator). The application of RbR MBPC resulted in an improved C/sub pk/ of 44% for aluminum sputter deposition, while reducing the number of lot-based monitor wafers by a factor of three. The application of RbR MBPC to the titanium sputter deposition process eliminated look-ahead test runs and reduced the number of monitor wafers by a factor of three. At the same time, C/sub pk/ was improved by 10% with the application of RbR MBPC.
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63 citations
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Journal Article• 10.1109/66.670160•
An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution
Jian Chen 1, Dennis Sylvester 1, Chenming Hu 1•Institutions (1)
University of California, Berkeley 1
01 Dec1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: In this paper, a simple, accurate method of measuring interconnect capacitances is presented, which is suitable for measurement-based, inter-connect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices.
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Abstract: A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 /spl mu/m, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.
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60 citations
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Journal Article• 10.1109/66.661294•
Critical area extraction for soft fault estimation
G.A. Allan 1, Anthony J. Walton 1•Institutions (1)
TL;DR: In this article, the Edinburgh yield estimator (EYE) is used to extract the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout.
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Abstract: Algorithms are presented for extracting the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout. These algorithms have been implemented within the Edinburgh Yield Estimator (EYE) tool which permits efficient extraction of the critical area from an arbitrary mask layout. Accurate estimates of device critical area of even the largest devices can be obtained in a reasonable time using the sampling version of the tool. The application of these algorithms to defect related reliability is explored and results reported that compare the susceptibility to soft faults before and after layout modifications intended to enhance manufacturing yield. These results suggest that yield enhancement techniques can have a significant impact on defect-related device reliability.
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55 citations
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Journal Article• 10.1109/66.670182•
Maintenance scheduling and staffing policies in a wafer fabrication facility
S. A. Mosley 1, T. Teyner 2, Reha Uzsoy 3•Institutions (3)
Intel 1, Harris Corporation 2, Purdue University 3
TL;DR: Results indicate that the choice of maintenance scheduling policy can significantly affect system performance under restrictive staffing-levels, and factory performance is shown to be sensitive to small changes in staffing level.
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Abstract: We examine how to reduce the adverse effects of machine down time by prioritizing production equipment for attention by a limited number of maintenance personnel. The maintenance scheduling policies use system information to determine which machines are the most critical at a given time. This information includes repair times, queue lengths, due dates, available capacity, and steady-state utilizations. The effects of different staffing levels are also considered. A discrete-event simulation model of a wafer fabrication facility is used to examine the performance of the different policies. Results indicate that the choice of maintenance scheduling policy can significantly affect system performance under restrictive staffing-levels. Moreover, factory performance is shown to be sensitive to small changes in staffing level.
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54 citations
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Journal Article• 10.1109/66.661290•
Soo-Young Lee 1, Brian D. Cook•Institutions (1)
TL;DR: This paper presents the hierarchical digital signal processing (DSP) model utilized by PYRAMID (the authors' proximity effect correction scheme) to estimate exposures and employs a two part hierarchical estimation technique which is several orders of magnitude faster than a direct (spatial domain or FFT-based) convolution yet is able to predict the result of an exposure with a high degree of accuracy.
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Abstract: One of the major limiting factors in electron beam (e-beam) lithography is the undesired development of circuit area caused by electron scattering (the proximity effect). Since the proximity effect imposes a severe limitation on the ultimate resolution attainable with electron beam lithography, it is important to examine ways in which the proximity effect can be reduced. In order to develop a fast and efficient proximity effect correction scheme it is necessary to have a fast and accurate technique for finding the exposure (energy) deposited at any given point in the circuit pattern. In this paper we present the hierarchical digital signal processing (DSP) model utilized by PYRAMID (our proximity effect correction scheme) to estimate these exposures. Our approach employs a two part hierarchical estimation technique which is several orders of magnitude faster than a direct (spatial domain or FFT-based) convolution yet is able to predict the result of an exposure with a high degree of accuracy. A detailed description of our method of exposure estimation is followed by a thorough analysts of its performance through simulation and experimental results.
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Journal Article• 10.1109/66.661289•
The effect of patterns on thermal stress during rapid thermal processing of silicon wafers
J.P. Hebb 1, Klavs F. Jensen 2•Institutions (2)
Eaton Corporation 1, Massachusetts Institute of Technology 2
TL;DR: In this paper, the transient temperature fields in patterned wafers are simulated using a detailed finite element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties.
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Abstract: The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform.
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Journal Article• 10.1109/66.705380•
J. Lee 1, A.S. Mack 1•Institutions (1)
Intel 1
TL;DR: In this article, the authors present an analysis of simple interconnection structures which contain two-level aluminum (Al) metal layers and a tungsten (W) via connection and discuss the effects on interconnection stress when intrinsic stresses in various layers are taken into account.
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Abstract: High levels of interconnection line stress are a serious reliability problem for the integrated circuit industry. These stresses, which are due to the thermal expansion coefficient difference between the line and its surroundings, as well as to nonequilibrium film growth, can lead to failure mechanisms such as voiding and cracking. Historically, stresses in these lines have typically been modeled using a fixed configuration at the final process step. The stresses are calculated as the model Is cooled to room temperature. We have developed models to calculate stresses in interconnection structures as a function of process step, such as film deposition, etching, and thermal cycles. During processing both thermal and intrinsic stresses are induced, and continuously changed by subsequent process steps. This paper presents such an analysis of simple interconnection structures which contain two-level aluminum (Al) metal layers and a tungsten (W) via connection. Stress histories of the metal and via layers are obtained and discussed. This paper also discusses the effects on interconnection stress when intrinsic stresses in various layers are taken into account.
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Journal Article• 10.1109/66.728563•
A probabilistic approach to run-to-run control
Eric S. Hamby 1, P.T. Kabamba 2, Pramod P. Khargonekar 2•Institutions (2)
University of Michigan 1, Technische Universität München 2
01 Nov1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: This paper considers model uncertainty in the run-to-run control problem from a probabilistic viewpoint and the Monte Carlo method is used to approximate the probability of performance to a high degree of confidence.
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Abstract: This paper considers model uncertainty in the run-to-run control problem from a probabilistic viewpoint. The methodology assumes that the model parameters are stochastic and uses experimental input-output data off-line to characterize the probability distribution of the model parameters. This naturally leads to the notions of probability of stability and probability of performance as a means of evaluating run-to-run controllers. Analytic formulas for the probability of stability are given for the particular case of an EWMA controller. When considering a more general notion of performance, the Monte Carlo method is used to approximate the probability of performance to a high degree of confidence. This probabilistic approach to run-to-run control is then illustrated on a virtual plasma etching reactor. Finally, the reliability of the method is investigated.
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Journal Article• 10.1109/66.661291•
PYRAMID-a hierarchical, rule-based approach toward proximity effect correction. II. Correction
Brian D. Cook 1, Soo-Young Lee 1•Institutions (1)
TL;DR: This paper presents the correction hierarchy employed in PYRAMID and analyzes its accuracy using both simulation and experimental results demonstrating PY RAMID's ability to correct circuit patterns with minimum feature sizes down to 0.1 /spl mu/m on homogeneous substrates successfully.
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Abstract: For pt. I see ibid., vol. 11, no. 1, p. 108-16 (1998). One of the major limiting factors with electron beam lithography in the production of high resolution patterns is the distortion of the exposed region by electron scattering. This distortion (known as the proximity effect) imposes a severe limitation on the ultimate resolution attainable with electron beam lithography. It is therefore important to examine ways in which the proximity effect can be reduced, we are currently developing a novel proximity effect correction scheme called PYRAMID which takes a hierarchical, rule-based approach toward correction. In Part I, our fast and accurate exposure estimation scheme is presented. In this paper (Part II), we present the correction hierarchy employed in PYRAMID and analyze its accuracy using both simulation and experimental results demonstrating PYRAMID's ability to correct circuit patterns with minimum feature sizes down to 0.1 /spl mu/m on homogeneous substrates successfully.
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Journal Article• 10.1109/66.705372•
Modeling and simulation of an electronic component manufacturing system using hybrid Petri nets
M. Allam 1, H. Alla 1•Institutions (1)
Centre national de la recherche scientifique 1
TL;DR: In this article, a hybrid Petri net is presented as a powerful tool for modeling and simulation of semiconductor manufacturing systems, which has been used for modeling a real-life electronic components manufacturing system.
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Abstract: Modelling and analysis for the design and operation of manufacturing systems is a vital need. For semiconductor manufacturing systems, which are large scale systems, discrete Petri nets do not constitute an adequate tool for modeling and analysis. In fact, use of discrete Petri nets is confronted with tile state explosion and the high cost of simulation. In this paper, hybrid Petri nets are presented as powerful tools for modeling and simulation of semiconductor manufacturing systems. This model has been used for modeling and simulation of a real life electronic components manufacturing system. It provides an accurate and first simulation of this system.
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Journal Article• 10.1109/66.705371•
MuDer Jeng 1, Xiaolan Xie, Shih Wei Chou•Institutions (1)
National Taiwan Ocean University 1
TL;DR: In this paper, a project of applying Petri net methodologies to detailed modeling, qualitative analysis, and performance evaluation of the etching area in a real-world IC wafer fabrication system located in Taiwan's Hsinchu Science-Based Industrial Park is reported.
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Abstract: Integrated circuit (IC) wafer fabrication systems can be characterized as discrete event systems. Petri nets are tools that have been successfully used to model and analyze such systems. This paper reports a project of applying Petri net methodologies to detailed modeling, qualitative analysis, and performance evaluation of the etching area in a real-world IC wafer fabrication system located in Taiwan's Hsinchu Science-Based Industrial Park, To tackle the problem of building a large and complex system model, a synthesis technique is used. The resultant extended net model is checked for important qualitative properties in manufacturing. A simple control policy for deadlock prevention is proposed. To obtain performance measures, simulation is used. The simulation result shows that except a small number of machines, the errors between the simulated and actual utilizations are less than 5%, The validated model can be used to answer many "what-if" questions, such as predicting the maximal throughput and bottleneck machines.
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Journal Article• 10.1109/66.670179•
Application of non-normal process capability indices to semiconductor quality control
Sergio Bittanti 1, Marco Lovera, L. Moiraghi•Institutions (1)
Polytechnic University of Milan 1
TL;DR: In this paper, a curve-fitting approach to the estimation problem is taken and the problem of providing confidence intervals for the estimates of PCI's is considered; some application examples are also presented.
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Abstract: The definition and estimation of process capability indices are usually based on the assumption that the production process under investigation is characterized by a normal distribution; however, the case of nonnormal processes occurs frequently in practice, as, for example, in the semiconductor industry. This paper addresses the problem of defining and computing reliable estimates for process capability indices (and particularly for C/sub pk/) for nonnormal processes; in particular, a curve-fitting approach to the estimation problem is taken and the problem of providing confidence intervals for the estimates of PCI's is considered. Finally, some application examples are also presented.
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Journal Article• 10.1109/66.705385•
Modelling tool for chemical-mechanical polishing design and evaluation
S.R. Runnels 1, I. Kim, J. Schleuter, C. Karlsrud, M. Desai - Show less +1 more•Institutions (1)
Southwest Research Institute 1
TL;DR: In this article, a wafer-scale material removal model is implemented in a chemical-mechanical polishing (CMP) modeling software environment called Plane-View, and a three-step model validation procedure is established where sets of material removal profiles are automatically read by PlaneView, which then adjusts the model parameters to optimize the model's fit.
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Abstract: Wafer-scale phenomenological modeling, combined with an automatic model validation algorithm, has been implemented in a chemical-mechanical polishing (CMP) modeling software environment called Plane-View. The wafer-scale material removal model is an enhanced Preston equation that admits a nonuniform pressure distribution. Automatic model validation is performed using the Levenberg-Marquart minimization scheme and film thickness data. A three-step model validation procedure is established where sets of material removal profiles are automatically read by Plane-View, which then adjusts the model parameters to optimize the model's fit, creates formulae that capture the behavior of those parameters as a function of process conditions, and stores formulae in a library for easy access by users. This article describes the software architecture, the wafer-scale model, the theoretical aspects of model validation, and a demonstration of the model and validation results using a set of five test wafers.
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Journal Article• 10.1109/66.670181•
Multiobjective scheduling for IC sort and test with a simulation testbed
Jian Yang 1, Tsu-Shuan Chang•Institutions (1)
University of California, Davis 1
TL;DR: A multiobjective model for IC sort and test is formulated, based upon the current information at any given instant, and an approximate Pareto boundary can be found using the Lagrangian relaxation method for the model.
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Abstract: In manufacturing environments such as an integrated circuit (IC) sort and test floor, typically more than one objective, such as cycle time and on-time delivery, needs to be simultaneously considered. With multiple objectives, a good solution is called Pareto optimal if it is not inferior to any other feasible solutions in terms of all objectives. The Pareto boundary is the set of all Pareto optimal solutions, which indicates the tradeoff of all good solutions. In this paper, a multiobjective model for IC sort and test is formulated, based upon the current information at any given instant. An approximate Pareto boundary can then be found using the Lagrangian relaxation method for the model. New algorithms are used to solve the dual problem and obtain feasible solutions from the associated subproblem solutions. The impact of the new scheduling approach on performance is illustrated through numerical examples by comparing it with corresponding single-objective problems and various heuristic dispatching rules. Its performance in dynamic and stochastic environments for real world applications is evaluated by using a simulation testbed. Simulation results definitely indicate a high potential for our approach.
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Journal Article• 10.1109/66.705376•
Modeling and emulation of a furnace in IC fab based on colored-timed Petri net
Sheng-Ya Lin 1, Han-Pang Huang•Institutions (1)
TL;DR: In this article, a colored timed Petri net (CTPN) is used to model the furnace and a hierarchical and modular CTPN model is built by dividing the behaviors of the furnace to make the model more compact and the modular modeling makes the model flexible and easy to use.
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Abstract: In integrated circuit (IC) manufacturing, the wafer processing takes more time in furnaces than other equipment. How to effectively integrate furnaces with other automated machines is very important. In particular, using the real furnace for testing not only introduces trouble but also wastes time. This paper aims to model and construct an emulation environment for the furnace. The colored timed Petri net (CTPN) is used to model the furnace. Based on CTPN, the dynamic behaviors of the furnace, such as loading, processing, unloading and wafer count mismatching, can be emulated. The proposed CTPN model is hierarchical and modular. The hierarchical architecture is built by dividing the behaviors of the furnace to make the model more compact and the modular modeling makes the model flexible and easy to use. On the other hand, the furnace emulator provides a quasi environment for testing so that potential problems of the system can be detected in advance and the testing time can be economized.
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Journal Article• 10.1109/66.728552•
Circuit sensitivity to interconnect variation
Z. Lin, Costas J. Spanos, L.S. Milor, Y.T. Lin
TL;DR: This work develops approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters and an accurate interconnect modeling technique is presented.
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Abstract: Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations.
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Proceedings Article• 10.1109/IWSTM.1998.729766•
Alessandra Nardi, Andrea Neviani 1, Enrico Zanoni 1, M. Quarantelli 2, C. Guardiani - Show less +1 more•Institutions (2)
University of Padua 1, University of Brescia 2
07 Jun1998- IEEE Transactions on Semiconductor Manufacturing
TL;DR: It is shown that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling.
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Abstract: The impact of process fluctuations on the variability of deep sub-micron (DSM) VLSI circuit performances is investigated in this paper. In particular, we show that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as in the assigned probability technique (APT) (Dal Fabbro et al, Proc. 32nd ACM/IEEE Design Automation Conf., pp. 702-6, 1995). The application of the APT technique to a 16-bit ripple-carry adder designed in 0.35 /spl mu/m, 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies with a power supply ranging from 3.3 V down to 1 V demonstrates how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high performance or low-power systems in 0.18 /spl mu/m and lesser technologies.
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Journal Article• 10.1109/66.728551•
Simulating the impact of pattern-dependent poly-CD variation on circuit performance
B.E. Stine 1, Duane S. Boning 1, J.E. Chung 1, Dennis Ciplickas 2, John Kibarian 2 - Show less +1 more•Institutions (2)
Massachusetts Institute of Technology 1, PDF Solutions 2
TL;DR: In this paper, the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance is simulated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout.
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Abstract: In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.
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Journal Article• 10.1109/66.670174•
A novel in situ monitoring technique for reactive ion etching using a surface micromachined sensor
M. D. Baker 1, F. R. Williams, Gary S. May•Institutions (1)
TL;DR: In this article, a micromachined sensor is used to measure the change in resonant frequency that occurs in a micro-achined platform during reactive ion etching, and the sensor is driven into resonance electrostatically and the shift in resonance is detected by monitoring the changes in impedance between the drive electrode and platform.
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Abstract: This paper presents a novel technique for monitoring film thickness in reactive ion etching by incorporating a micromachined sensor. The prototype sensor correlates film thickness with the change in resonant frequency that occurs in a micromachined platform during etching. The platform is suspended over a drive electrode on the surface of the substrate and electrically excited into resonance. As material is etched from the platform, its resonant vibrational frequency shifts by an amount proportional to the amount of material etched, allowing etch rate to be inferred. As a proof-of-concept experiment, a platform made of DuPont 2611 polyimide has been fabricated. The sensor is driven into resonance electrostatically, and the shift in resonance is detected by monitoring the change in impedance between the drive electrode and platform as the drive frequency is swept. To enhance filtering of the sensor signal in the noisy plasma environment, the platform is designed so that the ratio of the plasma frequency to the fundamental mode of vibration is approximately 400:1. The prototype was etched in a Plasma Therm 700 series reactive ion etching (RIE) system in a CHF/sub 3//O/sub 2/ plasma. Electrical contact was made with the sensor using a feedthrough attached to the vacuum line beneath the process chamber to facilitate in situ excitation and measurement. The sensor is shown to offer high resolution (approximately 1300 Hz/um), potentially permitting accurate in situ monitoring of etch rate and uniformity at a nominal cost.
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Journal Article• 10.1109/66.661287•
Lamp configuration design for rapid thermal processing systems
Yaw-Kuen Jan 1, Ching-An Lin•Institutions (1)
National Chiao Tung University 1
TL;DR: In this article, a configuration consisting of four concentric circular lamp zones, three of them above the wafer and one circumventing it, was considered and a method was proposed to determine the geometric parameters, the width, height and radius, of the lamp zones so that the configuration designed has the capacity to achieve a uniform temperature on the Wafer.
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Abstract: We have studied lamp configuration design for rapid thermal processing (RTP) systems. We considered a configuration consisting of four concentric circular lamp zones, three of them above the wafer and one circumventing the wafer. We propose a method to determine the geometric parameters, the width, height and radius, of the lamp zones so that the configuration designed has the capacity to achieve a uniform temperature on the wafer. The method is based on a necessary and sufficient condition for uniform temperature tracking and analytic expressions of the view factors. A design example is given in which a least square open-loop control law yields good temperature uniformity.
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Journal Article• 10.1109/66.670152•
Michael W. Cresswell, R.A. Allen, William F. Guthrie, J.J. Sniegowski, Rathindra N. Ghoshtagore, Loren W. Linholm - Show less +2 more
TL;DR: In this paper, the physical widths of reference features incorporated into electrical linewidth test structures patterned in films of monocrystalline silicon have been determined from Kelvin voltage measurements.
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Abstract: The physical widths of reference features incorporated into electrical linewidth test structures patterned in films of monocrystalline silicon have been determined from Kelvin voltage measurements. The films in which the test structures are patterned are electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide provided by SIMOX (Separation by the IMplantation of OXygen) processing. The motivation is to facilitate the development of linewidth reference materials for critical-dimension (CD) metrology-instrument calibration. The selection of the (110) orientation of the starting silicon and the orientation of the structures' features relative to the crystal lattice enable a lattice-plane-selective etch to generate reference-feature properties of rectangular cross section and atomically planar sidewalls. These properties are highly desirable for CD applications in which feature widths are certified with nanometer-level uncertainty for use by a diverse range of CD instruments. End applications include the development and calibration of new generations of CD instruments directed at controlling processes for manufacturing devices having sub-quarter-micrometer features.
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Journal Article• 10.1109/66.728554•
Hisako Sato 1, H. Kunitomo, K. Tsuneno, K. Mori, Hiroo Masuda - Show less +1 more•Institutions (1)
Hitachi 1
TL;DR: In this paper, the effect of statistical process variation on the 0.25-/spl mu/m CMOS performance has been accurately characterized by using a new calibrated TCAD methodology.
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Abstract: Effects of statistical process variation on the 0.25-/spl mu/m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF's (response surface functions) for threshold voltage (V/sub th/) and saturation drain current (I/sub ds/). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V/sub th/ and 3% error in I/sub ds/. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS /spl Delta/I/sub ds/ in the production process. Furthermore we have designed an optimized 0.25-/spl mu/m CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V/sub th/ and I/sub ds/ variations of the 0.25-/spl mu/m CMOS exhibit less than 10% I/sub ds/ variation in the production level process, which is similar to the value of 0.35-/spl mu/m CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-/spl mu/m device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication.
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Journal Article• 10.1109/66.670164•
Test structures to measure the heat capacity of CMOS layer sandwiches
M. von Arx 1, O. Paul 1, H. Baltes 1•Institutions (1)
TL;DR: In this article, thermal characterization microstructures were used to measure the heat capacity of CMOS thin film sandwiches and the propagation of heat waves in the structures was monitored, which provided the thermal conductivity and heat capacity.
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Abstract: We report novel thermal characterization microstructures to measure the heat capacity of CMOS thin film sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers and for the thermal management of integrated circuits. The test structures were fabricated using a commercial 2-/spl mu/m CMOS process, followed by maskless micromachining. The propagation of heat waves in the structures is monitored, which provides the thermal conductivity and heat capacity of CMOS thin film sandwiches. At 300 K, volumetric heat capacities of (1.71/spl plusmn/0.12)/spl times/10/sup 6/ Jm/sup -3/K/sup -1/ and (2.41/spl plusmn/1.88)/spl times/10/sup 6/ Jm/sup -3/K/sup -1/ were obtained for the sandwich of CMOS dielectrics and for the lower CMOS metal, respectively. These values do not deviate significantly from available bulk data of such materials.
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Journal Article• 10.1109/66.705381•
Systems of multiple cluster tools: configuration and performance under perfect reliability
M.J. Lopez 1, S.C. Wood•Institutions (1)
TL;DR: In this paper, the authors compare the throughput and cycle time of different systems that perform the same sequence of process steps, with the same total number of modules grouped in different ways into multiple cluster tools.
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Abstract: By extrapolating technological trends, one can expect future fabs to consist largely of highly reliable cluster tools. Such trends raise the issues of how cluster tools should be configured (i.e., how modules should be grouped together), and the impact of configuration on optimal lot size. This paper generates equation-based models to compare the throughput and cycle time of different systems that perform the same sequence of process steps, with the same total number of modules grouped in different ways into multiple cluster tools. The two extremes of the spectrum of possible cluster tool configurations are considered: the serial configuration, in which a wafer visits each module in the cluster tool, and the parallel configuration, in which all of the modules in the cluster tool are identical. The models predict the following for typical cluster tool parameters and process times. When all process step times are identical, systems of serial-configured tools can achieve the same throughputs with lower cycle times, as their parallel-configured counterparts. However, if process times in the sequence significantly differ from one another, then systems of parallel-configured tools may achieve lower cycle times than their serial-configured counterparts at high throughputs. Finally, the serial configuration significantly reduces the lot size required to achieve total throughput capacity.
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